Integrated circuits (ICs) can be designed from high level description (HDL) languages which describe behavior, and connectivity, between elements of the IC device. In the process of simulating the behavior of integrated circuits represented as netlists, it is often necessary to provide libraries of data structures which characterize a particular IC block. One such library is a delay table which characterizes the propagation delay of a signal from an input to an output of the IC block. Each propagation delay is based on a particular ramp input of the input signal at the block's input and a particular capacitance value loaded on the block's output.
A prior art implementation of such a delay table is described in a reference entitled "Input Slope Models & Synopsys Non-Linear Delay Table Analysis," (Version 1.2) by Timothy J. Ehrler, provided herewith. In which a 25.times.25 table of delay values is provided indexed by "output loading" ranging from 0.0 to 9.6 picofarads (pfs) and "input ramp" ranging from 0.0 to 4.8 nanosecons (ns). The table covers most load and ramp ranges of all timing relationships (rels), while at the same time including all relevant critical input ramp (CIR) points. Although this table and its associated indices have been determined to be sufficient to cover most timing relationships within a particular analyzed library, it is applicable only to those rels within those cells within that library, and it is not applicable to any other library.
Moreover, this table is also very costly in terms of resource usage, given that there are over 300 single stage rels within the sample library. One example rel requires only a 3.times.23 array within the 25.times.25 one, resulting in an 89 percent waste of table resources for this particular rel. Note also that the table area bounding the CIR is essentially broken up into 4 regions. This is due to the fact that fast and slow ramp areas are represented as planes which intersect at CIR, the load and ramp indices of which intersect CIR. The predetermined table is thus divided into four regions, two of which contain CIR.
A prior art implementation of a single-stage ISM (input slope model) delay model within a Synopsys NLD library specified a 25.times.25 table of delay values, linearly indexed by "output loading" (total.sub.-- output.sub.-- net.sub.-- capacitance) and "input ramp" (input.sub.-- net.sub.-- transition). This table covered most load and ramp ranges of all timing relationships (rels), while at the same time including all relevant critical input ramp (CIR) points. The inclusion of CIR points is critical to the delay table, since they define the "line" where the fast-ramp delay region's "plane" intersects the "slow ramp" delay region's "plane". As such, it also defines the regions for within which interpolation errors are the greatest.
As documented in the above referenced optimization specification, Input Slope Models & Synopsys Non-Linear Delay Table Analysis, the interpolation errors were most severe within the lowest load region. In order to reduce these errors, the table's sample points were forced to be closer together within this region. By using a non-linear distribution of table indices, these low load region errors were reduced, at the expense of only very slightly increasing interpolation errors in the highest load regions.
The prior art optimization process first determined the maximum capacitance the output pin is capable of driving, using is as the upper load limit with 0.0 being the lower. An interpolation delay table was then generated for 64 non-linearly indexed load points between 0.0 and the maximum capacitance, inclusive, with the ramp indices calculated as the critical input ramp values corresponding to the given load points. Delay tables were then generated in a similar manner, sequentially increasing the number of non-linearly indexed load points from 2 through 64 as required.
Since interpolation errors are the greatest along the critical input ramp, delay values interpolated along the CIR of the generated table were compared with those in the interpolation delay table, the latter's load and ramp indices being used as interpolation indices into the generated delay table. Delay table generation continued unit such time as the maximum absolute percentage of error from the calculated delay values along the CIR is not greater than 5%.
FIG. 1 outlines the described prior art optimization methodology 200. FIG. 2 shows the optimized 18.times.18 geometrically indexed delay table 205 for the example timing rel, illustrating the concentration of load/ramp indices within the lower load regions. Also shown is the 64.times.64 non-linearly indexed base array 230 over which interpolation error analysis to within 5% is performed. The smaller closely spaced grid lines 210 represent the interpolation delay table. The farther apart darker grid lines 220 represent the optimized delay table and the diagonal line 225 running through the outer represents the critical input ramp function.
FIG. 3 illustrates the interpolation errors for the optimized delay table with respect to the base array, the maximum absolute value of which is 4.61%. Note the higher absolute interpolated delay error percentage within the lower load and ramp regions as compared to those of the higher ones. In FIG. 3, the closely spaced grid 250 represents the optimized table interpolation error and the bottom running line 240 represents the critical input ramp interpolation error.
The prior art optimization specification employed a continuous non-linear distribution of table indices, successively generating ever larger delay tables until such time as the maximum error percentage along the critical input ramp was within 5%, or the generated table size was that of the interpolation comparison one. While this guaranteed that interpolated delay values within the optimized tables were within the maximum error percentage limit, it also resulted in the generation of tables much larger than necessary to satisfy error limit requirements in the upper load/ramp region, as can be seen in FIG. 3.
Accordingly, what is needed is a table is provides sufficient coverage while not consuming too much memory. What is needed further is a delay table that can be individually tailored to contain only enough points to include the CIR over the net's output load capacitance range. The present invention provides such a solution.